A/D conversion circuit and solid imaging device

ABSTRACT

An A/D conversion circuit 20 comprises a coupling capacitor C201, feedback capacitor C202, switch SW202, amplifier 201, comparison portion 202, capacitance control portion 203, and variable capacitance portions 210, 220, and 230. The variable capacitance portion 210 comprises capacitors C211 to C214 and switches SW211 to SW214. One end of each of the capacitors C211 to C214 is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the respective switches SW211 to SW214, to either the reference voltage Vref1 or to the common voltage Vcom.

TECHNICAL FIELD

This invention relates to an A/D conversion circuit which converts analog values into digital values, and a solid-state image pickup device comprising an A/D conversion circuit.

BACKGROUND ART

A solid-state image pickup device comprises a plurality of photodetector elements, arranged in a one-dimensional or two-dimensional array, and a plurality of integrating circuits which integrate the signal currents output from each photodetector element to convert the signal currents into voltages. In this solid-state image pickup device, signal currents with values corresponding to the incident light intensity are output from the plurality of photodetector elements, voltages corresponding to the integrated signal currents are output from the integrating circuits, and based on the voltages, the distribution of the incident light intensity is obtained, to capture an image. A solid-state image pickup device may further comprise an A/D conversion circuit to convert voltages (analog values) output from the integrating circuits into digital values. In this case, an incident light intensity is obtained as a digital value, and image processing by a computer or similar becomes possible.

One well-known configuration of an A/D conversion circuit comprises N combinations of capacitors and switches; of the N capacitors, the nth capacitor has a capacitance value of 2^(n−1) (N≧2, 1≦n≦N) . In this A/D conversion circuit, all capacitance values are set appropriately by appropriately setting the open/close states of each of the N switches according to the input analog value, so that an N-bit digital value corresponding to the open/close states of the N switches is output.

In such a solid-state image pickup device, faster operation and higher precision of the A/D conversion circuit are sought. In order to achieve faster operation, A/D conversion circuits are provided for each integrating circuit, to perform parallel processing. In order to increase precision, the number of bits of the digital value output from A/D conversion circuits is increased. Hence in order to improve both the processing speed and the precision of A/D conversion processing, an A/D conversion circuit may be provided for each integrating circuit to perform parallel processing, and the number of capacitors N in each A/D conversion circuit may be increased.

DISCLOSURE OF THE INVENTION

However, when attempting to fabricate a solid-state image pickup device comprising an A/D conversion circuit as described above on a single semiconductor chip, the following problems are encountered. The area occupied by capacitors on the chip is substantially proportional to the capacitance value. Hence if the number of bits is N, then the area occupied by N capacitors of an A/D conversion circuit is equivalent to the area occupied by one capacitor with capacitance value 2^(N)C (≈C+2C+2²C+. . . +2^(N−1)C) . That is, if the number of bits is increased by one, the area occupied by all the capacitors of the A/D conversion circuit increases by a factor of 2. Also, if the capacitance value of a capacitor is large, the parasitic capacitance also increases, and fast A/D conversion processing becomes impossible. Hence conventional solid-state image pickup devices comprising A/D conversion circuits encounter limits in attempting to improve both speed, by providing an integrating circuit for each A/D conversion circuit, and precision, by increasing the number of bits of the digital values output from A/D conversion circuits.

The present invention was devised in order to resolve the above problems, and it is an object of the invention to provide an A/D conversion circuit which, while occupying a small area, easily achieves both fast operation and high precision, as well as a solid-state image pickup device comprising this A/D conversion circuit.

An A/D conversion circuit of this invention converts an analog value input to an input end into a digital value and outputs this digital value from an output end, and is characterized in comprising: (1) an amplifier, having a first input terminal, a second input terminal and an output terminal, in which the first input terminal is connected to the input end via a coupling capacitor, and a common voltage V_(com) is input to the second input terminal; (2) a feedback capacitor, provided between the first input terminal and the output terminal of the amplifier; (3) a switch, provided between the first input terminal and the output terminal of the amplifier; (4) a number M of variable-capacitance portions, each having a number N_(m) of capacitors with different capacitance values, one end of each of which is connected to the first input terminal of the amplifier, and voltage switching means to switch the voltage input to each of the other ends of the N_(m) capacitors to a common voltage V_(com) and to P_(m) reference voltages V_(ref,m,1) to V_(ref,m,Pm) (M≧1, N_(m)≧1, P_(m)≧1, 1≦m≦M, but excluding the case M=P₁=1); (5) a comparison portion, which compares the magnitudes of the voltage output from the amplifier output terminal and the common voltage V_(com), and outputs a signal indicating-the comparison result; and, (6) a capacitance control portion, which controls the switching operation in each of the voltage switching means of the M variable-capacitance portions, and which outputs a digital value to the output terminal based on the switched state in the respective voltage switching means of the M variable-capacitance portions as well as the signal output from the comparison portion.

By means of this A/D conversion circuit, when the switch between the first input terminal and the output terminal of the amplifier is closed, the feedback capacitor between the first input terminal and the output terminal of the amplifier is discharged. When the switch is then opened and a voltage (analog value) for A/D conversion is input from the input end, electric charge corresponding to the input voltage integrates across the feedback capacitor. Then, either the common voltage V_(com) or one of the P_(m) reference voltages V_(ref,m,1) to V_(ref,m,Pm) is switched by the voltage switching means to each of the other ends of the N_(m) capacitors comprised by each of the M variable capacitance portions controlled by the capacitance control portion. One end of the N_(m) capacitors comprised by each of the M variable capacitance portions is connected to the first input terminal of the amplifier, either directly or via a switch, so that upon switching, charge moves from the feedback capacitor to the M variable capacitance portions. Then, a voltage corresponding to the amount of charge remaining in the feedback capacitor is output from the output terminal of the amplifier. The magnitude of the voltage output from the amplifier is compared with the common voltage V_(com) by the comparison portion, and a signal indicating the comparison result is output from the comparison portion to the capacitance control portion. Based on the switching states of the voltage switching means in each of the M variable capacitance portions and the signal output from the comparison portion, a digital value is output from the capacitance control portion to the output end.

In an A/D conversion circuit of this invention, it is preferable that M be 1, and that N₁ and P₁ be pluralities. In this case, the area occupied on the chip by the N_(m) capacitors comprised by each of the M variable capacitance portions is further reduced. In an A/D conversion circuit of this invention, it is preferable that M and N₁ each be 1, and that P₁ be a plurality; in this case, even compared with the above-described case, the area occupied on the chip by the N_(m) capacitors comprised by each of the M variable capacitance portions is further reduced.

A solid-state image pickup device of this invention is characterized in comprising (1) a photodetector element which outputs a signal current according to the incident light intensity; (2) an integrating circuit which inputs and integrates the signal current output from the photodetector element, and outputs a voltage corresponding to the integrated value of the signal current; and, (3) an A/D conversion circuit of this invention as described above, which inputs the voltage output from the integrating circuit, and converts this voltage into a digital value.

By means of this solid-state image pickup device, a signal current corresponding to the incident light intensity is output from the photodetector element, this signal current is input to and integrated by the integrating circuit, and a voltage corresponding to the integrated value is output from the integrating circuit. The voltage output from the integrating circuit is converted into a digital value by an A/D conversion circuit of this invention, described above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing of the configuration of a solid-state image pickup device 1 comprising an A/D conversion circuit 20 of a first embodiment;

FIG. 2 is a circuit diagram of the integrating circuit 10;

FIG. 3 is a circuit diagram of the A/D conversion circuit 20 of the first embodiment;

FIG. 4 is a table indicating the relation between the voltage V_(in) input to the A/D conversion circuit 20 and the values of the four bits D₁₁ to D₈;

FIG. 5 is a table indicating the relation between the voltage V₁ and the values of the four bits D₇ to D₄;

FIG. 6 is a table indicating the relation between the voltage V₂ and the values of the four bits D₃ to D₀;

FIG. 7 is a circuit diagram of the A/D conversion circuit 20 of a second embodiment;

FIG. 8 is a circuit diagram of the A/D conversion circuit 20 of a third embodiment; and,

FIG. 9 is a circuit diagram of a reference voltage generation circuit.

BEST MODES FOR CARRYING OUT THE INVENTION

Below, embodiments of this invention are explained in detail, referring to the attached drawings. In explanations of the drawings, the same components are assigned the same symbols, and redundant explanations are omitted.

(First Embodiment)

The first embodiment of the invention is explained. FIG. 1 is a drawing of the configuration of a solid-state image pickup device 1 comprising an A/D conversion circuit 20 of the first embodiment. This solid-state image pickup device 1 comprises K units U₁ to U_(K) (where K is an integer equal to or greater than 1); each unit U_(K) (where k is an arbitrary integer greater than or equal to 1, and less than or equal to K) has a plurality of combinations of photodiodes (photodetector elements) PD and switches SW, an integrating circuit 10, an A/D conversion circuit 20, and a switch SW1. The solid-state image pickup device I comprises a reference voltage supply circuit 30 and control circuit 40.

In each unit U_(k), each photodiode PD is grounded at the anode, while the cathode is connected to the input end of the integrating circuit 10 via the switch SW; a signal current corresponding to the incident light intensity is output to the integrating circuit 10. The integrating circuit 10 inputs and integrates the signal current output from the photodiode PD, and outputs a voltage corresponding to the integrated value of this signal current. The A/D conversion circuit 20 inputs the voltage output from the integrating circuit 10, converts this voltage (analog value) into a 12-bit digital value (D₁₁ through D₀), and outputs this digital value to the switch SW1.

The reference voltage supply circuit 30 supplies a reference voltage to the A/D conversion circuits 20 of each of the units U_(k). The control circuit 40 controls the opening and closing of the switches SW provided between each photodiode PD and integrating circuit 10, and is connected in succession to each photodiode PD and integrating circuit 10. The control circuit 40 controls the opening and closing of the switches SW1 provided after the A/D conversion circuits 20, and outputs digital values in succession to each unit U_(k). The control circuit 40 controls the opening and closing of the respective switches comprised by the integrating circuits 10 and switches comprised by the A/D conversion circuits 20, to cause the desired operation to occur.

FIG. 2 is a circuit diagram of an integrating circuit 10. In the integrating circuit 10, an amplifier A₁₀, capacitor C₁₀ and switch SW₁₀ are provided in parallel between the input end and output end. The capacitor C₁₀ is provided between the input terminal and the output terminal of the amplifier A₁₀, and when the switch SW₁₀ is open integrates the signal current, that is, electric charge, input to the input end. The switch SW₁₀ is provided between the input terminal and the output terminal of the amplifier A₁₀, and when open causes charge to integrate in the capacitor C₁₀, but when closed resets the integration of charge in the capacitor C₁₀.

FIG. 3 is a circuit diagram of the A/D conversion circuit 20 of the first embodiment. This A/D conversion circuit 20 comprises a coupling capacitor C₂₀₁, feedback capacitor C₂₀₂, switch SW₂₀₂, amplifier 201, comparison portion 202, capacitance control portion 203, and variable capacitance portions 210, 220 and 230.

The amplifier 201 inputs the voltage (analog value) output from the integrating circuit 10 to the inverted input terminal via the coupling capacitor C₂₀₁, and inputs the common voltage V_(com) to the non-inverted input terminal. The feedback capacitor C₂₀₂ is provided between the inverted input terminal and output terminal of the amplifier 201, and integrates charge according to the input voltage. The switch SW₂₀₂ is provided between the inverted input terminal and the output terminal of the amplifier 201, and when open causes charge to integrate in the feedback capacitor C₂₀₂, but when closed resets the charge integration in the feedback capacitor C₂₀₂. The amplifier 201 outputs, from the output terminal to the comparison portion 202, a voltage corresponding to the charge amount integrated in the feedback capacitor C₂₀₂. The comparison circuit 202 inputs the voltage output from the amplifier 201 to the inverted input terminal, inputs the common voltage V_(com) to the non-inverted input terminal, compares the magnitudes of the two input signals, and outputs a signal indicating the comparison result to the capacitance control portion 203.

The variable capacitance portion 210 comprises four capacitors C₂₁₁ to C₂₁₄ and four switches SW₂₁₁ to SW₂₁₄ (voltage switching means). One end of the capacitor C₂₁₁ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₁₁, to either the reference voltage V_(ref1) or to the common voltage V_(com). One end of the capacitor C₂₁₂ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₁₂, to either the reference voltage V_(ref1) or to the common voltage V_(com). One end of the capacitor C₂₁₃ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₁₃, to either the reference voltage V_(ref1) or to the common voltage V_(com). And, one end of the capacitor C₂₁₄ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₁₄, to either the reference voltage V_(ref1) or to the common voltage V_(com).

The variable capacitance portion 220 comprises four capacitors C₂₂₁ to C₂₂₄ and four switches SW₂₂₁ to SW₂₂₄ (voltage switching means). One end of the capacitor C₂₂₁ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₂₁, to either the reference voltage V_(ref2) or to the common voltage V_(com). One end of the capacitor C₂₂₂ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₂₂, to either the reference voltage V_(ref2) or to the common voltage V_(com) one end of the capacitor C₂₂₃ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₂₃, to either the reference voltage V_(ref2) or to the common voltage V_(com). And, one end of the capacitor C₂₂₄ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₂₄, to either the reference voltage V_(ref2) or to the common voltage V_(com).

The variable capacitance portion 230 comprises four capacitors C₂₃₁ to C₂₃₄ and four switches SW₂₃₁ to SW₂₃₄ (voltage switching means) . One end of the capacitor C₂₃₁ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₃₁, to either the reference voltage V_(ref3) or to the common voltage V_(com). One end of the capacitor C₂₃₂ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₃₂, to either the reference voltage V_(ref3) or to the common voltage V_(com). One end of the capacitor C₂₃₃ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₃₃, to either the reference voltage V_(ref3) or to the common voltage V_(com). And, one end of the capacitor C₂₃₄ is connected to the inverted input terminal of the amplifier 201, and the other end is connected, via the switch SW₂₃₄, to either the reference voltage V_(ref3) or to the common voltage V_(com).

The capacitance values of the capacitors, coupling capacitors C₂₀₁, and feedback capacitors C₂₀₂ comprised by each of the variable capacitance portions 210, 220 and 230 satisfy the following relations.

C ₂₀₁ =C ₂₀₂=16C  (1a)

C ₂₁₁ =C ₂₂₁ =C ₂₃₁=8C  (1b)

C ₂₁₂ =C ₂₂₂ =C ₂₃₂=4C  (1c)

C ₂₁₃ =C ₂₂₃ =C ₂₃₃=2C  (1d)

C ₂₁₄ =C ₂₂₄ =C ₂₃₄ =C  (1e)

Here C is a certain constant capacitance value. The reference voltage V_(ref1) supplied to the variable capacitance portion 210, the reference voltage V_(ref2) supplied to the variable capacitance portion 220, the reference voltage V_(ref3) supplied to the variable capacitance portion 230, and the common voltage V_(com) satisfy the following relations.

V _(ref2) −V _(com)=(V _(ref1) −V _(com))/16  (2a)

V _(ref3) −V _(com)=(V _(ref) ₂ −V _(com))/16  (2b)

Because the common voltage V_(com) is generally taken to be ground potential, hereafter it is assumed that V_(com)=0. Then, the above equations (2a), (2b) are expressed as follows.

V _(ref2) =V _(ref1)/16  (3a)

V _(ref3) =V _(ref2)/16  (3b)

Each of these reference voltages V_(ref1), V_(ref2) and V_(ref3) is supplied by the reference voltage supply circuit 30. The reference voltage supply circuit 30 is, for example, a voltage-dividing circuit in which resistors are connected in series.

The capacitance control portion 203 controls switching operation of the switch elements SW₂₁₁ to SW₂₁₄, SW₂₂₁ to SW₂₂₄, and SW₂₃₁ to SW₂₃₄. The capacitance control portion 203 stores the switched states of each of these 12 switches, and based on these switched states and on the signal output from the comparison portion 202, outputs a 12-bit digital value (D₁₁ to D₀). That is, the uppermost bit D₁₁ of the digital value output from the capacitance control portion 203 corresponds to the switched state of the switch SW₂₁₁; the bit D₁₀ corresponds to the switched state of the switch SW₂₁₂; the bit D₉ corresponds to the switched state of the switch SW₂₁₃; the bit D₈ corresponds to the switched state of the switch SW₂₁₄; the bit D₇ corresponds to the switched state of the switch SW₂₂₁; the bit D₆ corresponds to the switched state of the switch SW₂₂₂; the bit D₅ corresponds to the switched state of the switch SW₂₂₃; the bit D₄ corresponds to the switched state of the switch SW₂₂₄; the bit D₃ corresponds to the switched state of the switch SW₂₃₁; the bit D₂ corresponds to the switched state of the switch SW₂₃₂; the bit D₁ corresponds to the switched state of the switch SW₂₃₃; and, the lowermost bit D₀ corresponds to the switched state of the switch SW₂₃₄.

Next, operation of the solid-state image pickup device 1 and A/D conversion circuit 20 of the first embodiment is explained. In each unit U_(k), the signal current output from a photodiode PD is input to the integrating circuit 10 via a switch SW, and by integrating charge in the capacitor C₁₀ of this integrating circuit 10, a voltage corresponding to the input signal current is output. The voltage V_(in), output from the integrating circuit 10 is input to the A/D conversion circuit 20. In this A/D conversion circuit 20, the voltage V_(in) is converted into a digital value (D₁₁ to D₀). Up to this point, the units U_(k) operate in parallel. Then the switches SW1 of each unit U_(k) close in succession, and the digital values output from the A/D conversion circuit 20 of each unit U_(k) are output in succession from each unit U_(k).

The A/D conversion circuit 20 of each unit U_(k) operates as follows. In the first stage of the A/D conversion processing, the switch SW₂₀₂ is closed, and the feedback capacitor C₂₀₂ is discharging. Further, each of the switches SW₂₁₁ to SW₂₁₄, SW₂₂₁ to SW₂₂₄, and SW₂₃₁ to SW₂₃₄ is switched to the side of the common voltage V_(com). Then, the switch SW₂₀₂ is opened, and a charge amount Q corresponding to the voltage V_(in) output from the integrating circuit 10 is integrated in the feedback capacitor C₂₀₂. The charge amount Q is then expressed by the following equation.

Q=C ₂₀₂ ·V _(in)=16C·V _(in)  (4)

Thereafter, actual A/D conversion processing is initiated.

In the second stage of A/D conversion processing, switching of the four switches SW₂₁₁ to SW₂₁₄ comprised by the variable capacitance portion 210 is performed. First, the switch SW₂₁₁ corresponding to the capacitor C₂₁₁ having the largest capacitance value among the four capacitors C₂₁₁ to C₂₁₄ is switched to the reference voltage V_(ref1). As a result, the charge amount Q₂₁₁, which is a part of the charge Q integrated in the feedback capacitor C₂₀₂ (eq. (4)), moves to the capacitor C₂₁₁, the charge amount Q₂₁₁ being expressed by the following equation:

Q ₂₁₁ =C ₂₁₁ ·V _(ref1)=8C·V _(ref1)  (5)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C \cdot V_{i\quad n}}} - {8{C \cdot V_{ref1}}}}} \\ {= {16{C\left( {V_{i\quad n} - {V_{ref1}/2}} \right)}}} \end{matrix} & (6) \end{matrix}$

Also, the voltage (V_(in)−V_(ref1)/2) is output from the amplifier 201. The magnitudes of the voltage (V_(in)−V_(ref1)/2) input from the inverted input terminal of the amplifier 201 and the common voltage V_(com)(=0) input from the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V_(in)−V_(ref1)/2) is judged. The result is input to the capacitance control portion 203, and is stored as the value of the uppermost bit D₁₁ for output. That is, if the voltage (V_(in)−V_(ref1)/2) is positive, then D₁₁ is set to 1, and otherwise D₁₁ is set to 0.

If the voltage (V_(in)−V_(ref1)/2) is positive, the switch SW₂₁₂ corresponding to the capacitor C₂₁₂ with the next-largest capacitance is switched to the reference voltage V_(ref1). As a result, of the charge Q₂₀₂ which had been integrated in the feedback capacitor C₂₀₂ (eq. (6)), the charge amount Q₂₁₂ represented by the following equation moves to the capacitor C₂₁₂.

Q ₂₁₂ =C ₂₁₂ ·V _(ref1)=4C·V _(ref1)  (7)

Also, at this time the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C\left( {V_{i\quad n} - {V_{ref1}/2}} \right)}} - {4{C \cdot V_{ref1}}}}} \\ {= {16{C\left( {V_{i\quad n} - {3{V_{ref1}/4}}} \right)}}} \end{matrix} & (8) \end{matrix}$

Then, the voltage (V_(in)−3V_(ref1)/4) is output from the amplifier 201. The magnitudes of the voltage (V_(in)−3V_(ref1)/4) input from the amplifier 201 to the inverted input terminal and the common voltage V_(com) (=0) input to the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V_(in)−3V_(ref1)/4) is judged. The result is input to the capacitance control portion 203 and is stored as the value of the bit D₁₀ for output. That is, if the voltage (V_(in)−3V_(ref1)/4) is positive then D₁₀ is set to 1, and otherwise D₁₀ is set to 0.

If the voltage (V_(in)−3V_(ref1)/4) is positive, the switch SW₂₁₃ corresponding to the capacitor C₂₁₃ with the next-largest capacitance is switched to the reference voltage V_(ref1). As a result, of the charge Q₂₀₂ integrated in the feedback capacitor C₂₀₂ (eq. (8)), the charge amount Q₂₁₃ expressed by the following equation moves to the capacitor C₂₁₃.

Q ₂₁₃ =C ₂₁₃ ·V _(ref1)=2C·V _(ref1)  (9)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C\left( {V_{i\quad n} - {3{V_{ref1}/4}}} \right)}} - {2{C \cdot V_{ref1}}}}} \\ {= {16{C\left( {V_{i\quad n} - {7{V_{ref1}/8}}} \right)}}} \end{matrix} & (10) \end{matrix}$

Then, the voltage (V_(in)−7V_(ref1)/8) is output from the amplifier 201. The magnitudes of the voltage (V_(in)−7V_(ref1)/8) input from the amplifier 201 to the inverted input terminal and the common voltage V_(com) (=0) input to the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V_(in)−7V_(ref1)/8) is judged. The result is input to the capacitance control portion 203 and is stored as the value of the bit D₉ for output. That is, if the voltage (V_(in)−7V_(ref1)/8) is positive then D₉ is set to 1, and otherwise D₉ is set to 0.

On the other hand, if in determining the value of the uppermost bit D₁₁ the voltage (V_(in)−V_(ref1)/2) is negative, the switch SW₂₁₁ returns to the common voltage V_(com), and all of the charge amount Q (eq. (4)) returns to the feedback capacitor C₂₀₂. Then, the switch SW₂₁₂ corresponding to the capacitor C212 with the next-largest capacitance is switched to the reference voltage V_(ref1).

By this means, of the charge Q integrated in the feedback capacitor C₂₀₂ (eq. (4)), the charge amount Q₂₁₂ expressed by the following equation moves to the capacitor C₂₁₂.

Q ₂₁₂ =C ₂₁₂ ·V _(ref1)=4C·V _(ref1)  (11)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C \cdot V_{i\quad n}}} - {4{C \cdot V_{ref1}}}}} \\ {= {16{C\left( {V_{i\quad n} = {V_{ref1}/4}} \right)}}} \end{matrix} & (12) \end{matrix}$

Then, the voltage (V_(in)−V_(ref1)/4) is output from the amplifier 201. The magnitudes of the voltage (V_(in)−V_(ref1)/4) input to the inverted input terminal from the amplifier 201 and the common voltage V_(com) (=0) input to the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V_(in)−V_(ref1)/4) is judged. The result is input to the capacitance control portion 203, and is stored as the value of the bit D₁₀ for output. In other words, if the voltage (V_(in)−V_(ref1)/4) is positive then D₁₀ is set to 1, and otherwise D₁₀ is set to 0.

In this way, the switched states of the four switches SW₂₁₁ to SW₂₁₄ comprised by the variable capacitance portion 210 are determined in succession, and the values of the bits D₁₁ to D₈ are determined in succession.

FIG. 4 is a table showing the relations between the voltage V_(in) input to the A/D conversion circuit 20 and the values of the four bits D₁₁ to D₈. At the time at which the values of these four bits D₁₁ to D₈ are determined, the charge amount Q₁ remaining in the feedback capacitor C₂₀₂ is equal to or less than C·V_(ref1), and the voltage V₁ output from the amplifier 201 is V_(ref1)/2⁴ or less, which is a residue insufficient for A/D conversion in the above-described second stage.

In the third stage following the above-described second stage of A/D conversion processing, the charge amount Q₁ remaining in the feedback capacitor C₂₀₂ at the time the second-stage processing ends is subjected to processing similar to that of the second stage through switching operations of the four switches SW₂₂₁ to SW₂₂₄ comprised by the variable capacitance portion 220. That is, first the switch SW₂₂₁ corresponding to the capacitor C₂₂₁ with the largest capacitance among the four capacitors C₂₂₁ to C₂₂₄ is switched to the reference voltage V_(ref2). As a result, of the charge Q₁ integrated in the feedback capacitor C₂₀₂, the charge amount Q₂₂₁ expressed by the following equation moves to the capacitor C₂₂₁.

Q ₂₂₁ =C ₂₂₁ ·V _(ref2)=8C·V _(ref2)  (13)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C \cdot V_{1}}} - {8{C \cdot V_{ref2}}}}} \\ {= {16{C\left( {V_{1} - {V_{ref2}/2}} \right)}}} \end{matrix} & (14) \end{matrix}$

Then, the voltage (V₁−V_(ref2)/2) is output from the amplifier 201. The magnitudes of the voltage (V₁−V_(ref2)/2) input to the inverted input terminal from the amplifier 201 and the common voltage V_(com) (=0) input to the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V₁−V_(ref2)/2) is judged. The result is input to the capacitance control portion 203, and is stored as the value of the bit D₇ for output. If the voltage (V₂−V_(ref2)/2) is positive then D₇ is set to 1, and otherwise D₇ is set to 0. That is, if the voltage (V₁−V_(ref1)/32) is positive then D₇ is set equal to 1, and otherwise D₇ is set equal to 0.

In subsequent processing similarly, the switched states of the four switches SW₂₂₁ to SW₂₂₄ comprised by the variable capacitance portion 220 are determined in succession, and the values of the bits D₇ to D₄ are determined in succession. FIG. 5 is a table showing the relations between the voltage V₁ and the values of the four bits D₇ to D₄. At the time at which the values of these four bits D₇ to D₄ are determined, the charge amount Q₂ remaining in the feedback capacitor C₂₀₂ is less than or equal to C·V_(ref2) (less than or equal to C·V_(ref1)/2⁴), and the voltage V₂ output from the amplifier 201 is less than or equal to V_(ref2)/2⁴ (less than or equal to V_(ref1)/2⁸), which is a residue insufficient for A/D conversion in the above-described third stage.

In the fourth stage following the above-described third stage of A/D conversion processing, the charge amount Q₂ remaining in the feedback capacitor C₂₀₂ at the time the third-stage processing ends is subjected to processing similar to that of the second stage through switching operations of the four switches SW₂₃₁ to SW₂₃₄ comprised by the variable capacitance portion 230. That is, first the switch SW₂₃₁ corresponding to the capacitor C₂₃₁ with the largest capacitance among the four capacitors C₂₃₁ to C₂₃₄ is switched to the reference voltage V_(ref3). As a result, of the charge Q₁ integrated in the feedback capacitor C₂₀₂, the charge amount Q₂₃₁ expressed by the following equation moves to the capacitor C₂₃₁.

Q ₂₃₁ =C ₂₃₁ ·V _(ref3)=8C·V _(ref3)  (15)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C \cdot V_{2}}} - {8{C \cdot V_{ref3}}}}} \\ {= {16{C\left( {V_{2} - {V_{ref3}/2}} \right)}}} \end{matrix} & (16) \end{matrix}$

Then, the voltage (V₂−V_(ref3)/2) is output from the amplifier 201. The magnitudes of the voltage (V₂−V_(ref3)/2) input to the inverted input terminal from the amplifier 201 and the common voltage V_(com) (=0) input to the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V₂−V_(ref3)/2) is judged. The result is input to the capacitance control portion 203, and is stored as the value of the bit D₃ for output. If the voltage (V₂−V_(ref3)/2) is positive then D₃ is set to 1, and otherwise D₃ is set to 0. That is, if the voltage (V₂−V_(ref1)/512) is positive then D₃ is set equal to 1, and otherwise D₃ is set equal to 0.

In subsequent processing similarly, the switched states of the four switches SW₂₃₁ to SW₂₃₄ comprised by the variable capacitance portion 230 are determined in succession, and the values of the bits D₃ to D₀ are determined in succession. FIG. 6 is a table showing the relations between the voltage V₂ and the values of the four bits D₃ to D₀. At the time at which the values of these four bits D₃ to D₀ are determined, the charge amount Q₃ remaining in the feedback capacitor C₂₀₂ is less than or equal to C·V_(ref3) (less than or equal to C·V_(ref1)/2⁸), and the voltage V₃ output from the amplifier 201 is less than or equal to V_(ref3)/2⁴ (less than or equal to V_(ref1)/2¹²), which is a residue insufficient for A/D conversion even in the above-described fourth stage.

At the time the above-described fourth stage of A/D conversion processing ends, a 12-bit digital value D₁₁ to D₀ corresponding to the switched states of the 12 switches SW₂₁₁ to SW₂₁₄, SW₂₂₁ to SW₂₂₄, and SW₂₃₁ to SW₂₃₄ are stored in the capacitance control portion 203. After the fourth-stage processing ends, the 12 bits of digital values D₁₁ to D₀ are output from the capacitance control portion 203.

In this A/D conversion circuit 20, the area occupied on the chip by all of the capacitors and feedback capacitor portions C₂₀₂ comprised by the variable capacitance portions 210, 220 and 230 are equivalent to the area occupied by a capacitor with the capacitance value 61C (=3(8C+4C+2C+C)+16C). On the other hand, in a conventional A/D conversion circuit which outputs 12-bit digital values, the area occupied by the 12 capacitors is equivalent to the area occupied by one capacitor with a capacitance of 2¹²C. Thus the area occupied by capacitors in an A/D conversion circuit 20 of this invention is only {fraction (1/67)} that of a device of the prior art.

Hence in the case of a solid-state image pickup device 1 comprising such an A/D conversion circuit 20 occupying a small area, the speed of operation can be increased by providing an A/D conversion circuit 20 for each integrating circuit 10, and the precision can be improved by increasing the number of bits of digital values output from the A/D conversion circuits 20. The resolution also can be improved by increasing the number of photodiodes PD. Further, whereas the maximum capacitance value in a conventional A/D conversion circuit is 2¹¹C, the maximum capacitance value in an A/D conversion circuit 20 of this embodiment is 16C, so that there is little parasitic capacitance in an A/D conversion circuit 20 of this invention; for this reason also, the speed of A/D conversion processing can be increased.

(Second Embodiment)

Next, a second embodiment of the invention is explained. Compared with the case of the first embodiment, the solid-state image pickup device of the second embodiment differs in the configuration of the A/D conversion circuit 20.

FIG. 7 is a circuit diagram of the A/D conversion circuit 20 of the second embodiment. This A/D conversion circuit 20 comprises a coupling capacitor C₂₀₁, feedback capacitor C₂₀₂, switch SW₂₀₂, amplifier 201, comparison portion 202, capacitance control portion 203, and variable capacitance portion 240.

The amplifier 201 inputs the voltage (analog value) output from the integrating circuit 10 to the inverted input terminal via the coupling capacitor C₂₀₁, and inputs the common voltage V_(com) to the non-inverted input terminal. The feedback capacitor C₂₀₂ is provided between the inverted input terminal and the output terminal of the amplifier 201, and integrates charge according to the input voltage. The switch SW₂₀₂ is provided between the inverted input terminal and the output terminal of the amplifier 201, and when open causes charge to be integrated in the feedback capacitor C₂₀₂, but when closed resets the charge integration in the feedback capacitor C₂₀₂. The amplifier 201 outputs a voltage corresponding to the charge amount integrated in the feedback capacitor C₂₀₂ from the output terminal to the comparison portion 202. The comparison portion 202 inputs the voltage output from the amplifier 201 to the inverted input terminal, inputs the common voltage V_(com) to the non-inverted input terminal, compares the magnitudes of these two input signals, and outputs a signal indicating the comparison result to the capacitance control portion 203.

The capacitance control portion 240 comprises, in addition to four capacitors C₂₄₁ to C₂₄₄ and four switches SW₂₄₁ to SW₂₄₄ (voltage switching means), the switches SW₂₄₁₁, SW₂₄₁₂, SW₂₄₂₁, SW₂₄₂₂, SW₂₄₃₁, SW₂₄₃₂, SW₂₄₄₁, and SW₂₄₄₂. One end of the capacitor C₂₄₁ is connected to the inverted input terminal of the amplifier 201 via the switch SW₂₄₁₁, and this end is set to the common voltage V_(com) via the switch SW₂₄₁₂; the other end is connected, via the switch SW₂₄₁, to one of the reference voltages V_(ref1), V_(ref2) or V_(ref3), or to the common voltage V_(com). One end of the capacitor C₂₄₂ is connected to the inverted input terminal of the amplifier 201 via the switch SW₂₄₂₁, and this end is set to the common voltage V_(com) via the switch SW₂₄₂₂; the other end is connected, via the switch SW₂₄₂, to one of the reference voltages V_(ref1), V_(ref2) or V_(ref3), or to the common voltage V_(com). One end of the capacitor C₂₄₃ is connected to the inverted input terminal of the amplifier 201 via the switch SW₂₄₃₁, and this end is set to the common voltage V_(com) via the switch SW₂₄₃₂; the other end is connected, via the switch SW₂₄₃, to one of the reference voltages V_(ref1), V_(ref2) or V_(ref3), or to the common voltage V_(com). And, one end of the capacitor C₂₄₄ is connected to the inverted input terminal of the amplifier 201 via the switch SW₂₄₄₁, and this end is set to the common voltage V_(com) via the switch SW₂₄₄₂; the other end is connected, via the switch SW₂₄₄, to one of the reference voltages V_(ref1), V_(ref2) or V_(ref3), or to the common voltage V_(com).

The capacitance values of each of the capacitors, the coupling capacitor C₂₀₁, and the feedback capacitor C₂₀₂ comprised by the variable capacitance portion 240 satisfy the following relations.

C ₂₀₁ =C ₂₀₂=16c  (17a)

C ₂₄₁=8C  (17b)

C ₂₄₂=4C  (17c)

C ₂₄₃=2C  (17d)

C ₂₄₄ =C  (17e)

Here C is a certain constant capacitance value. Also, the reference voltages V_(ref1), V_(ref2) and V_(ref3) as well as the common voltage V_(com) supplied to the variable capacitance portion 240 satisfy eq. (2). Because the common voltage V_(com) is generally taken to be ground potential, hereafter it is assumed that V_(com)=0. The reference voltages V_(ref1), V_(ref2) and V_(ref3) are each supplied by the reference voltage supply circuit 30.

The capacitance control portion 203 controls the switching operation of each of the switches SW₂₄₁ to SW₂₄₄. The capacitance control portion 203 stores the switched states of these four switches, and outputs a 12-bit digital value (D₁₁ to D₀) based on these switched states and on a signal output from the comparison portion 202.

Next, the operation of the A/D conversion circuit 20 of the second embodiment is explained. In the first stage of A/D conversion processing, the switch SW₂₀₂ is closed, and the feedback capacitor C₂₀₂ is discharged. Each of the switches SW₂₄₁ to SW₂₄₄ is switched to the common voltage V_(com). The switches SW₂₄₁₁, SW₂₄₂₁, SW₂₄₃₁ and SW₂₄₄₁, are all closed; the switches SW₂₄₁₂, SW₂₄₂₂, SW₂₄₃₂, and SW₂₄₄₂ are all open. The switch SW₂₀₂ is then opened, and a charge amount Q corresponding to the voltage V_(in) output from the integrating circuit 10 integrates in the feedback capacitor C₂₀₂. Here the charge amount Q is expressed by eq. (4). After this, the actual A/D conversion processing is initiated.

In the second stage of A/D conversion processing, the four switches SW₂₄₁ to SW₂₄₄ comprised by the variable capacitance portion 240 are each switched between the reference voltage V_(ref1) and the common voltage V_(com). This switching operation is similar to that of the second stage in the first embodiment. When this second stage processing ends, the switched states of each of the four switches SW₂₄₁ to SW₂₄₄ comprised by the variable capacitance portion 240 (between either the reference voltage V_(ref1) or the common voltage V_(com)) are determined in succession, and the values of the bits D₁₁ to D₈ are determined in succession. The relations between the voltage V_(in) input to the A/D conversion circuit 20 and the values of the four bits D₁₁ to D₈ are similar to those indicated in FIG. 4. At the time at which the values of these four bits D₁₁ to D₈ are determined, the charge amount Q₁ remaining in the feedback capacitor C₂₀₂ is equal to or less than C·V_(ref1), and the voltage V₁ output from the amplifier 201 is equal to or less than V_(ref1)/24, which is a residue insufficient for A/D conversion in the above-described second stage.

Following the above-described second-stage A/D conversion processing, the switches SW₂₄₁₁, SW₂₄₂₁, SW₂₄₃₁ and SW₂₄₄₁, are each opened, the switches SW₂₄₁₂, SW₂₄₂₂, SW₂₄₃₂ and SW₂₄₄₂ are each closed, the switches SW₂₄₁ to SW₂₄₄ are each switched to the common voltage V_(com), and the capacitors C₂₂₁ to C₂₂₄ are each discharged. Then the switches SW₂₄₁₂, SW₂₄₂₂, SW₂₄₃₂ and SW₂₄₄₂ are each opened, and the switches SW₂₄₁₁, SW₂₄₂₁, SW₂₄₃₁ and SW₂₄₄₁ are each closed. Following this, the third stage of A/D conversion processing is initiated.

In the third stage of A/D conversion processing, the charge amount Q₁ remaining in the feedback capacitor C₂₀₂ at the time the second-stage processing ends is subjected to switching operations of the four switches SW₂₄₁ to SW₂₄₄ comprised by the variable capacitance portion 240 between the reference voltage V_(ref2) and the common voltage V_(com). This switching operation is similar to that of the third stage in the first embodiment. Then, when the third-stage processing is completed, the switched states (to either the reference voltage V_(ref2) or to the common voltage V_(com)) of each of the four switches SW₂₄₁ to SW₂₄₄ comprised by the variable capacitance portion 240 are determined in succession, and the values of the bits D₇ to D₄ are determined in succession. The relations between the voltage V₁ and the values of the four bits D₇ to D₄ are similar to those indicated in FIG. 5. When the values of these four bits D₇ to D₄ are determined, the charge amount Q₂ remaining in the feedback capacitor C₂₀₂ is equal to or less than C·V_(ref2), and the voltage V₂ output from the amplifier 201 is equal to or less than V_(ref2)/2⁴, which is a residue insufficient for A/D conversion in the above-described third stage.

Following the above-described third-stage A/D conversion processing, the switches SW₂₄₁₁, SW₂₄₂₁, SW₂₄₃₁ and SW₂₄₄₁ are each opened, the switches SW₂₄₁₂, SW₂₄₂₂, SW₂₄₃₂ and SW₂₄₄₂ are each closed, the switches SW₂₄₁ to SW₂₄₄ are each switched to the common voltage V_(com), and the capacitors C₂₂₁ to C₂₂₄ are each discharged. Then the switches SW₂₄₁₂, SW₂₄₂₂, SW₂₄₃₂ and SW₂₄₄₂ are each opened, and the switches SW₂₄₁₁, SW₂₄₂₁, SW₂₄₃₁, and SW₂₄₄₁, are each closed. Following this, the fourth stage of A/D conversion processing is initiated.

In the fourth stage of A/D conversion processing, the charge amount Q₂ remaining in the feedback capacitor C₂₀₂ at the time the third-stage processing ends is subjected to switching operations of the four switches SW₂₄₁ to SW₂₄₄ comprised by the variable capacitance portion 240 between the reference voltage V_(ref3) and the common voltage V_(com). This switching operation is similar to that of the fourth stage in the first embodiment. Then, when the fourth-stage processing is completed, the switched states (to either the reference voltage V_(ref3) or to the common voltage V_(com)) of each of the four switches SW₂₄₁ to SW₂₄₄ comprised by the variable capacitance portion 240 are determined in succession, and the values of the bits D₃ to D₀ are determined in succession. The relations between the voltage V₂ and the values of the four bits D₃ to D₀ are similar to those indicated in FIG. 6. When the values of these four bits D₃ to D₀ are determined, the charge amount Q₃ remaining in the feedback capacitor C₂₀₂ is equal to or less than C·V_(ref3), and the voltage V₃ output from the amplifier 201 is equal to or less than V_(ref3)/2⁴, which is a residue insufficient for A/D conversion even in the above-described third-stage.

At the time the above-described fourth stage of A/D conversion processing ends, a 12-bit digital value D₁₁ to D₀ corresponding to the switched states of the 4 switches SW₂₄₁ to SW₂₄₄ for the cases of each of the three reference voltages V_(ref1) to V_(ref3) are stored in the capacitance control portion 203. After the fourth-stage processing ends, the 12 bits of digital values D₁₁ to D₀ are output from the capacitance control portion 203.

In this A/D conversion circuit 20, the area occupied on the chip by all of the capacitors and feedback capacitor portion C₂₀₂ comprised by the variable capacitance portion 240 are equivalent to the area occupied by a capacitor with the capacitance value 31C (=8C+4C+2C+C+16C) . On the other hand, in a conventional A/D conversion circuit which outputs 12-bit digital values, the area occupied by the 12 capacitors is equivalent to the area occupied by one capacitor with a capacitance of 2¹²C. Thus the area occupied by capacitors in an A/D conversion circuit 20 of this invention is only {fraction (1/132)} that of a device of the prior art, and only ½ the area occupied by the capacitors in the first embodiment.

(Third Embodiment)

Next, a third embodiment of this invention is explained. Compared with the first embodiment, the configurations of both the A/D conversion circuit 20 and the reference voltage supply circuit 30 of the solid-state image pickup device of the third embodiment are different. FIG. 8 is a circuit diagram of the A/D conversion circuit 20 of the third embodiment. This A/D conversion circuit 20 comprises a coupling capacitor C₂₀₁, feedback capacitor C₂₀₂, switch SW₂₀₂, amplifier 201, comparison portion 202, capacitance control portion 203, and variable capacitance portion 250.

The amplifier 201 inputs the voltage (analog value) output from the integrating circuit 10 into the inverted input terminal via the coupling capacitor C₂₀₁, and inputs the common voltage V_(com) to the non-inverted input terminal. The feedback capacitor C₂₀₂ is provided between the inverted input terminal and the output terminal of the amplifier 201, and integrates charge according to the input voltage. The switch SW₂₀₂ is provided between the inverted input terminal and the output terminal of the amplifier 201, and when open causes charge to integrate in the feedback capacitor C₂₀₂, but when closed resets the charge integration in the feedback capacitor C₂₀₂. The amplifier 201 outputs a voltage corresponding to the charge amount integrated in the feedback capacitor C₂₀₂ from the output terminal to the comparison portion 202. The comparison circuit 202 inputs the voltage output from the amplifier 201 to the inverted input terminal, inputs the common voltage V_(com) to the non-inverted input terminal, compares the magnitudes of the two input signals, and outputs a signal indicating the comparison result to the capacitance control portion 203.

The variable capacitance portion 250 comprises, in addition to a capacitor C₂₅₀ and switch SW₂₅₀ (voltage switching means), the switches SW₂₅₁, and SW₂₅₂. One end of the capacitor C₂₅₀ is connected to the inverted input terminal of the amplifier 201 via the switch SW₂₅₁, and the other end is connected, via the switch SW₂₅₀, to either one of the reference voltages V_(ref1) to V_(ref12), or to the common voltage V_(com).

The capacitance values of the capacitor C₂₅₀, coupling capacitor C₂₀₁, and feedback capacitor C₂₀₂ comprised by the variable capacitance portion 250 satisfy the following relations.

C ₂₀₁ =C ₂₀₂=16C  (18a)

C ₂₅₀=8C  (18b)

Here C is a certain constant capacitance value. The reference voltages V_(ref1) to V_(ref12) and the common voltage V_(com) satisfy the following relations.

V _(ref2) −V _(com)=(V _(ref1) −V _(com))/2  (19a)

V _(ref3) −V _(com)=(V _(ref2) −V _(com))/2  (19b)

V _(ref4) −V _(com)=(V _(ref3) −V _(com))/2  (19c)

V _(ref5) −V _(com)=(V _(ref4) −V _(com))/2  (19d)

V _(ref6) −V _(com)=(V _(ref5) −V _(com))/2  (19e)

V _(ref7) −V _(com)=(V _(ref6) −V _(com))/2  (19f)

V _(ref8) −V _(com)=(V _(ref7) −V _(com))/2  (19g)

V _(ref9) −V _(com)=(V _(ref8) −V _(com))/2  (19h)

V _(ref10) −V _(com)=(V _(ref9) −V _(com))/2  (19i)

V _(ref11) −V _(com)=(V _(ref10) −V _(com))/2  (19j)

V _(ref12) −V _(com)=(V _(ref11) −V _(com))/2  (19k)

Because the common voltage V_(com) is generally taken to be ground potential, hereafter it is assumed that V_(com)=0. Also, the reference voltages V_(ref1) to V_(ref12) are each supplied by the reference voltage supply circuit 30. The reference voltage supply circuit 30 is, for example, a voltage-dividing circuit in which resistors are connected in series.

The capacitance control portion 203 controls the switching operation of the switch SW₂₅₀. Also, the capacitance control portion 203 stores the switched state of the switch SW₂₅₀, and outputs a 12-bit digital value (D₁₁ to D₀) based on this switched state and on a signal output from the comparison portion 202.

Next, the operation in the A/D conversion circuit 20 of the third embodiment is explained. In the first stage of A/D conversion processing, the switch SW₂₀₂ is closed, and the feedback capacitor C₂₀₂ is discharged. The switch SW₂₅₀ is switched to the common voltage V_(com). The switch SW₂₅₁ is closed, and the switch SW₂₅₂ is open. Then, the switch SW₂₀₂ is opened, and a charge amount Q corresponding to the voltage V_(in) output from the integrating circuit 10 integrates in the feedback capacitor C₂₀₂. Here the charge amount Q is expressed by eq. (4). Then, the actual A/D conversion processing is initiated.

In the second stage of A/D conversion processing, switching of the switches SW₂₅₀ comprised by the variable capacitance portion 250 between the reference voltage V_(ref1) and the common voltage V_(com) is performed. That is, the switch SW₂₅₀ is switched to the reference voltage V_(ref1). As a result, of the charge Q integrated in the feedback capacitor C₂₀₂ (eq. (4)), the charge amount Q₂₅₀ expressed by the following equation moves to the capacitor C₂₅₀.

Q ₂₅₀ =C ₂₅₀ ·V _(ref1)=8C·V _(ref1)  (20)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C \cdot V_{i\quad n}}} - {8{C \cdot V_{ref1}}}}} \\ {= {16{C\left( {V_{i\quad n} - {V_{ref1}/2}} \right)}}} \end{matrix} & (21) \end{matrix}$

Then, the voltage (V_(in)−V_(ref1)/2) is output from the amplifier 201. The magnitudes of the voltage (V_(in)−V_(ref1)/2) input from the inverted input terminal of the amplifier 201 and the common voltage V_(com) (=0) input from the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V_(in)−V_(ref1)/2) is judged. The result is input to the capacitance control portion 203, and is stored as the value of the uppermost bit D₁₁ for output. That is, if the voltage (V_(in)−V_(ref1)/2) is positive, then D₁₁ is set to 1, and otherwise D₁₁ is set to 0. When the value of this bit D₁₁, is determined, the charge amount Q₁ remaining in the feedback capacitor C₂₀₂ is equal to or less than C·V_(ref1), and the voltage V₁ output from the amplifier 201 is equal to or less than V_(ref1)/2, which is a residue insufficient for A/D conversion in the above-described second stage.

After the above-described second stage of A/D conversion processing, the switch SW₂₅₁ is opened, the switch SW₂₅₂ is closed, the switch SW₂₅₀ is switched to the common voltage V_(com), and the capacitor C₂₅₀ is discharged. Then the switch SW₂₅₂ is opened, and the switch SW₂₅₁ is closed. After this, the third stage of A/D conversion processing is initiated.

In the third stage of A/D conversion processing, the charge amount Q₁ remaining in the feedback capacitor C₂₀₂ at the time the second-stage processing ends is subjected to switching operations of the switch SW₂₅₀ comprised by the variable capacitance portion 250 between the reference voltage V_(ref2) and the common voltage V_(com). That is, the switch SW₂₅₀ is switched to the reference voltage V_(ref2). As a result, of the charge Q₁ integrated in the feedback capacitor C₂₀₂, the charge amount Q₂₅₀ expressed by the following equation moves to the capacitor C₂₅₀.

Q ₂₅₀ =C ₂₅₀ ·V _(ref2)=4C·V _(ref1)  (22)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C \cdot V_{1}}} - {4{C \cdot V_{ref1}}}}} \\ {= {16{C\left( {V_{1} - {V_{ref1}/2^{2}}} \right)}}} \end{matrix} & (23) \end{matrix}$

Then, the voltage (V₁−V_(ref1)/2²) is output from the amplifier 201. The magnitudes of the voltage (V₁−V_(ref1)/2²) input from the inverted input terminal of the amplifier 201 and the common voltage V_(com) (=0) input from the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V₁−V_(ref1)/2²) is judged. The result is input to the capacitance control portion 203, and is stored as the value of the bit D₁₀ for output. That is, if the voltage (V₁−V_(ref1)/2²) is positive, then D₁₀ is set to 1, and otherwise D₁₀ is set to 0. When the value of this bit D₁₀ is determined, the charge amount Q₂ remaining in the feedback capacitor C₂₀₂ is equal to or less than C·V_(ref1)/2, and the voltage V₂ output from the amplifier 201 is equal to or less than V_(ref1)/2², which is a residue insufficient for A/D conversion in the above-described third stage.

After the above-described third stage of A/D conversion processing, the switch SW₂₅₁ is opened, the switch SW₂₅₂ is closed, the switch SW₂₅₀ is switched to the common voltage V_(com), and the capacitor C₂₅₀ is discharged. Then the switch SW₂₅₂ is opened and the switch SW₂₅₁ is closed. After this, the fourth stage of A/D conversion processing is initiated.

In the fourth stage of A/D conversion processing, the charge amount Q₂ remaining in the feedback capacitor C₂₀₂ at the time the third-stage processing ends is subjected to switching operations of the switch SW₂₅₀ comprised by the variable capacitance portion 250 between the reference voltage V_(ref3) and the common voltage V_(com). That is, the switch SW₂₅₀ is switched to the reference voltage V_(ref3). As a result, of the charge Q₂ integrated in the feedback capacitor C₂₀₂, the charge amount Q₂₅₀ expressed by the following equation moves to the capacitor C₂₅₀.

Q ₂₅₀ =C ₂₅₀ ·V _(ref3)=2C·V _(ref1)  (24)

At this time, the charge amount Q₂₀₂ expressed by the following equation remains in the feedback capacitor C₂₀₂. $\begin{matrix} \begin{matrix} {Q_{202} = {{16{C \cdot V_{1}}} - {2{C \cdot V_{ref1}}}}} \\ {= {16{C\left( {V_{1} - {V_{ref1}/2^{3}}} \right)}}} \end{matrix} & (25) \end{matrix}$

Then, the voltage (V₂−V_(ref1)/2³) is output from the amplifier 201. The magnitudes of the voltage (V₂−V_(ref1)/2³) input from the inverted input terminal of the amplifier 201 and the common voltage V_(com) (=0) input from the non-inverted input terminal are compared by the comparison portion 202, and the sign of the voltage (V₂−V_(ref1)/2³) is judged. The result is input to the capacitance control portion 203, and is stored as the value of the bit D₉ for output. That is, if the voltage (V₂−V_(ref1)/2³) is positive, then D₉ is set to 1, and otherwise D₉ is set to 0. When the value of this bit D₉ is determined, the charge amount Q₃ remaining in the feedback capacitor C₂₀₂ is equal to or less than C·V_(ref1)/2², and the voltage V₃ output from the amplifier 201 is equal to or less than V_(ref1)/2³ , which is a residue insufficient for A/D conversion in the above-described fourth stage.

After the above-described fourth stage of A/D conversion processing, the switch SW₂₅₁ is opened, the switch SW₂₅₂ is closed, the switch SW₂₅₀ is switched to the common voltage V_(com), and the capacitor C₂₅₀ is discharged. Then the switch SW₂₅₂ is opened and the switch SW₂₅₁ is closed. After this, the fifth stage of A/D conversion processing is initiated.

The fifth and subsequent stages of A/D conversion processing are similar. In the 13th stage of A/D conversion processing, the charge amount remaining in the feedback capacitor C₂₀₂ at the end of the 12th stage of processing is subjected to switching of the switch SW₂₅₀ comprised by the variable capacitance portion 250 between the reference voltage V_(ref12) and the common voltage V_(com). In this 13th stage, the value of the lowermost bit D₀ is stored in the capacitance control portion 203.

When the above-described 13th stage of A/D conversion processing ends, a 12-bit digital value D₁₁ to D₀, corresponding to the switched states of the switch SW₂₅₀ in each of the cases of the 12 levels of reference voltages V_(ref1) to V_(ref12), is stored in the capacitance control portion 203. After the end of the 13th stage of processing, this 12-bit digital value D₁₁ to D₀ is output from the capacitance control portion 203.

In this A/D conversion circuit 20, the area occupied on the chip by all of the capacitors and the feedback capacitor C₂₀₂ comprised by the variable capacitance portion 240 is equivalent to the area occupied by one capacitor with capacitance value 24C (=8C+16C). On the other hand, in a conventional A/D conversion circuit which outputs 12-bit digital values, the area occupied by the 12 capacitors is equivalent to the area occupied by one capacitor with a capacitance value of 2¹²C. Thus the area occupied by capacitors in the A/D conversion circuit 20 of this embodiment is {fraction (1/170)} that of the prior art, and is ⅖ the area occupied by capacitors in the first embodiment.

(Modified Embodiment)

In general, the number M of variable capacitance portions comprised by an A/D conversion circuit of this invention is 1 or greater, the number N_(m) of capacitors comprised by the mth variable capacitance portion (1≦m≦M) among the M variable capacitance portions is 1 or greater, and the number of levels of reference voltages P_(m) input to the other end (on the side opposite the end connected to the input terminal of the amplifier) of the respective N_(m) capacitors comprised by the mth variable capacitance portion is 1 or greater. However, the case of M=P₁=1 is excluded. If the capacitance values of the N_(m) capacitors comprised by the mth variable capacitance portion are C_(m,1) to C_(m,Nm), and the reference voltages supplied to the mth variable capacitance portion are V_(ref,m,1) to V_(ref,m,Pm), then for each m value, each n value (1≦n≦N_(m)), and each p value (1≦p≦P_(m)), values are chosen such that each value of C_(m,n)·V_(ref,m,p) is different. Further, it is preferable that each value of C_(m,n)·V_(ref,m,p), when arranged in an ascending series, constitute a geometric progression the common ratio of which is 2. The number of bits of the digital value output from the A/D conversion circuit is expressed by the following equation.

N ₁ ·P ₁ +N ₂ ·P ₂ + . . . +N _(M)·P_(M)  (26)

In each of the above embodiments, the number of bits of the digital value output from the A/D conversion circuit was 12; but any arbitrary number may be used. In the above-described first embodiment, M=3, N_(m)=4 for each, and P_(m)=1 for each; but in general, M may be an arbitrary number equal to or greater than 2, and each N_(m) may also be an arbitrary number each to or greater than 2. In the above-described second embodiment, M=1, N₁=4, and P₁=3; but in general, N₁ may be an arbitrary number equal to or greater than 2, and P₁ may also be an arbitrary number equal to or greater than 2. In this case, the area occupied on the chip by the N₁ capacitors is smaller still. In the above-described third embodiment, M=1, N₁=1, and P₁=12; but in general, P₁ may be an arbitrary number equal to or greater than 2, and in this case the area occupied on the chip by the single capacitor is smaller still. Further, M may be greater than 1, and for each value of N_(m) may be 1 and P_(m) may be 1. M may be greater than 1, each value of N_(m) may differ, and each value of P_(m) may differ as well.

FIG. 9 is a circuit diagram of a reference voltage generation circuit which generates the above-described reference voltages V_(refk) (k=1,2,3, . . . ). The voltage of the common voltage generation circuit SVG is divided into multiple values by series resistors (R1, R2, . . . , Rk). Each of the divided voltage outputs is captured as a reference voltage V_(refk) via a buffer amplifier BA.

Industrial Applicability

This invention can be utilized in an A/D conversion circuit which converts analog values into digital values, and in a solid-state image pickup device comprising this A/D conversion circuit. 

What is claimed is:
 1. An A/D conversion circuit, which converts an analog value input at the input end into a digital value and outputs the digital value at the output end, comprising: an amplifier having a first input terminal, second input terminal, and output terminal, said first input terminal of which is connected to said input end via a coupling capacitor, and to said second input terminal of which is input a common voltage V_(com); a feedback capacitor, provided between said first input terminal and said output terminal of said amplifier; a switch, provided between said first input terminal and said output terminal of said amplifier; a number M of variable capacitance portions, each having a number N_(m) of capacitance elements one end of each of which is connected to said first input terminal of said amplifier and having different capacitance values, and voltage switching means which switches a voltage for input to the other end of the respective said N_(m) capacitors, between said common voltage V_(com) and any of a number P_(m) of reference voltages V_(rgf,m,1) to V_(ref,m,Pm), wherein M≧1, N_(m)≧1, P_(m)≧1, 1≦m≦M, but excluding the case M=P₁=1; a comparison portion, which compares the magnitudes of the voltage output from said output terminal of said amplifier and said common voltage V_(com), and outputs a signal indicating the comparison result; and, a capacitance control portion, which controls the switching operations of each of said voltage switching means of said M variable capacitance portions, and which outputs to said output end a digital value based on the switched states of each of said voltage switching means of said M variable capacitance portions as well as on the signal output from said comparison portion.
 2. The A/D conversion circuit according to claim 1, wherein M is 1, and N₁ and P₁ are each 2 or more.
 3. The A/D conversion circuit according to claim 1, wherein M and N₁ are each 1, and P₁ is 2 or more.
 4. A solid-state image pickup device, comprising: a photodetector element, which outputs a signal current corresponding to the incident light intensity; an integrating circuit, which inputs and integrates the signal current output by said photodetector element, and outputs a voltage corresponding to the integrated value of the signal current; and, the A/D conversion circuit according to claim 1, which inputs the voltage output by said integrating circuit, and converts the voltage to a digital value. 